1. Field of the Invention
The present invention relates to a method for fabricating a pattern and further relates to a method for manufacturing a semiconductor device using the method for fabricating a pattern.
2. Description of the Related Art
A gate structure of a metal oxide semiconductor (MOS) transistor is formed by the following process steps. First, for example, a thin gate oxide film is formed on a p-type silicon (Si) substrate, and a polysilicon thin film is deposited on the gate oxide film. Then, a photoresist is coated on the polysilicon thin film and is patterned using a photolithography technique to form a gate mask pattern. Thereafter, the polysilicon thin film and the gate oxide film are selectively etched using the gate mask pattern by means of reactive ion etching (RIE), thereby forming a gate structure. Since the RIE is a directional etching, the polysilicon thin film and the gate oxide film are etched in a vertical direction relative to an etching mask and therefore, the gate structure is formed to have the same pattern dimensions as the gate mask pattern.
However, in accordance with recent higher integration and higher speed operation of a semiconductor device, a shorter gate length is increasingly in demanded and therefore, the above-described photolithography technique alone cannot address requirements for achieving a finer pattern because of resolution limitation due to the wavelength of a light source of an aligner. Therefore, a method for fabricating a pattern has been employed in which a mask pattern is first fabricated using the photolithography technique and then the mask pattern is etched by an isotropic etching process using a reactive gas species generated by a plasma or the like so as to reduce a pattern width. However, in a process to reduce the pattern width of the mask pattern, typically, the pattern width is adjusted by controlling an etching time of the isotropic etching process. In more detail, the etching rate of the isotropic etching process was previously calculated based on several preliminary experiments, and then a reduced width of the mask pattern has been determined by controlling an etching time provided from the etching rate. Accordingly, unexpected variations in etching conditions in the reduction process of the mask pattern decreases controllability and reproducibility of the reduced width of the mask pattern, which results in variations in the pattern width of the gate structure.
Furthermore, to measure a pattern width of a fine mask pattern, a Scanning Electron Microscope (SEM) is typically used. When performing an SEM measurement, a semiconductor substrate needs to be loaded into a vacuum chamber of the SEM, which means that the SEM measurement is not a simple task. Moreover, when performing an SEM measurement, high-energy beams are used and, therefore, the mask pattern is damaged. In view of the above described problems, it is desirable to perform measurement of the pattern width by using an optical method.
As described above, in the reduction process of the mask pattern for a gate structure and the like, the reduced width of the mask pattern is adjusted by controlling the etching time. Therefore, it is difficult to improve controllability and reproducibility of the reduced width or productivity of the reduction process of the mask pattern.